This invention relates to a designing method aiming power integrity of a semiconductor chip included in a semiconductor package and to a design aid system and a computer program product in both of which the method is implemented.
In a semiconductor chip such as a dynamic random access memory (DRAM) chip, transient currents flow through a power supply pad and a ground pad of the semiconductor chip, for example, when an output driver of the semiconductor chip changes its output state, i.e. from high level to low level, or from low level to high level. The transient currents cause voltage fluctuations at the power supply pad and the ground pad.
If the above-mentioned voltage fluctuations exceed a certain level, the semiconductor chip fails to function properly. Therefore, a semiconductor package should be designed so that the above-mentioned voltage fluctuations do not exceed the voltage fluctuation limitation.
In order to verify whether voltage fluctuations are allowable, a transient analysis with a SPICE (Simulation Program with Integrated Circuit Emphasis) model is conventionally carried out as disclosed in JP-A 2004-54522. When a user finds out as a result of the conventional transient analysis that a designed semiconductor package violates the voltage fluctuation limitation therefor, the user should carry out design modification such as layout modification on the previously-designed package and then carry out a transient analysis on a newly-designed package, again. Normally, the above-mentioned analysis and design modification is carried out multiple times by trial and error, in accordance with the conventional transient analysis, so that its design cycle needs long time.
JP-A 2005-198406 has proposed another approach. The disclosed approach includes an analysis not in time domain but in frequency domain; the analysis is carried out on a fine layout to be formed on a semiconductor chip. However, the disclosed analysis cannot be carried out on a semiconductor package that comprises an already-designed semiconductor chip.